Design-For-Test (DFT) Engineer
Accenture — Hyderabad
Posted 2026-10-23
Project Role : Design-For-Test (DFT) Engineer Project Role Description : Enable effective post-manufacturing chip testing by integrating testability features during the design phase. Apply DFT methodologies such as scan chains, Built-In Self-Test (BIST), and boundary scan to detect defects and enhance test coverage. Ensure high-quality silicon by collaborating with design and verification teams to optimize for test efficiency and fault isolation. Must have skills : Design for Testability (DFT) Good to have skills : NA Minimum 7.5 year(s) of experience is required Educational Qualification : 15 years full time education Summary: Architect, implement, and validate innovative DFT techniques. Insert DFT logic into SoC / Sub-system at RTL or Gate level. Know how to validate all DFT features at RTL or Gate level, generate ATE targeted test patterns and how to perform Silicon diagnostic. As a Design-For-Test Engineer, your day involves ensuring that integrated circuits are designed with features that facilitate thorough and efficient testing after manufacturing. You will work closely with various teams to embed testability elements into chip designs, enabling early detection of defects an